AnalogX Launches Ultra Low Power Interconnect SerDes IP Portfolio to Fuel Next-Generation I/O Connectivity

Toronto, April 21, 2019 - AnalogX Inc., a Canadian corporation, is delighted to unveil its new, silicon-proven, multi-protocol, 1 to 33Gbps AXLinkIO connectivity IP portfolio. The AXLinkIO portfolio of Serializer/Deserializer interconnect IP solutions is ideally suited for high-bandwidth chiplets and chips in AI processors, 5G networking, optical interfaces, and datacenter computing. The IP architecture has been delivered to customers and has been silicon proven in a leading 16/12nm process technology.  AXLinkIO exhibits the world’s lowest power, lowest area, and highest performance for any interconnect SerDes IP architecture running up to 33Gbps.

The AXLinkIO portfolio of IPs includes AXDieIO, AXLinkIO-SR, and AXlinkIO-MR IP solutions. AXDieIO targets chiplet die-to-die applications, while AXLinkIO-SR and AXLinkIO-MR target chip-to-chip, chip-to-module and multi-chip connectivity. All IPs utilize the same silicon-proven AXLinkIO architecture featuring world-class signal and power integrity for multi-terabit, high transceiver lane count applications. The AXLinkIO IPs support a multitude of standard interface protocols such as PCIe Gen1-5, JESD, OIF, CPRI, Ethernet and others.

“We’ve spent nearly two decades designing high-end, multi-protocol SerDes IP solutions for volume production and we are extremely passionate and committed in delivering truly innovative, silicon-proven technology. Compared to other solutions in this segment, we are providing our customers with exponential differentiation in terms of power, area density, and performance,” said Robert Wang, Co-Founder and CEO. “Our team is really proud to have breached the 1 mW/Gbps power barrier in 16/12nm and our newer developments are on pace to further improve our power and area density, while maintaining our excellent and robust performance.”

The AXLinkIO portfolio of IPs operate continuously from 1 to 33Gbps, while supporting hundreds of transceiver lanes per die side without stacking. The IP architecture delivers unprecedented power consumption, down to 1mW/Gbps in die-to-die applications. All AX IPs exhibit the world’s best area, IO density, and latency in the segment class. Multiple lane configurations are available for all AX IPs, along with comprehensive IP deliverables, user-friendly configuration software and world-class support to ensure seamless and easy IP integration.

AnalogX will demonstrate the AXLinkIO IP architecture at DAC 2019 (booth 862) in Las Vegas, USA, June 2nd to 6th.

About AnalogX Inc.

AnalogX Inc. ( develops cutting-edge, connectivity IP solutions for premier technology companies.  Founded in 2017 by industry veterans in the interconnect space, AnalogX’s mission is to enable high-end, mixed-signal IPs that drive revolutionary SoC designs for high-bandwidth applications that range from AI to Data Center Computing.  AnalogX is headquartered in Toronto, Canada.


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Come visit us at DAC2019, Booth 862 in Las Vegas this summer!