OVERVIEW

The AXLinkIO MR IP utilizes the silicon-proven AXLinkIO transceiver architecture for medium-reach and PCIe type of channel links.

APPLICATIONS

  • Tailored and optimized for processor, Chip-to-Chip, and Chip-to-Module connectivity

TECHNICAL HIGHLIGHTS

  • 1 - 33 Gbps continuous operation

  • World’s best power, area and latency in segment

  • Channel loss support up to 25dB

  • Supports both AC and DC

  • Standard two supplies and devices

  • Supports any lane configuration up to x20 per macro

  • Compatible with many protocols including PCIe Gen1-5, JESD, OIF, CPRI, Ethernet, and others

  • No external components nor special packaging requirements

  • Integrates seamlessly with extensive test & configuration software and features

  • Available in advanced FINFET technology