The AXLinkIO C2C IP utilizes the silicon-proven AXLinkIO transceiver architecture for chip-to-chip type of channel links.


  • Tailored and optimized for processor, Chip-to-Chip, and Chip-to-Module connectivity


  • 1 - 33 Gbps continuous operation

  • 1.8 mW/Gbps

  • World’s best area and latency in segment

  • Channel loss support up to 18dB

  • Supports both AC and DC

  • Standard two supplies and devices

  • Supports any lane configuration up to x20 per macro

  • Compatible with several short-reach protocols

  • No external components nor special packaging requirements

  • Integrates seamlessly with extensive test & configuration software and features

  • Available in advanced FINFET technology