Overview

The AXDieIO IP utilizes the silicon-proven AXLinkIO transceiver architecture for die-to-die, in package, type of channel links.

Applications

  • Tailored and optimized for AI interconnect, Die-to-Die and chiplet connectivity

TECHNICAL HighLights

  • 1 - 33 Gbps continuous operation

  • 1 mW/Gbps

  • World’s best area and latency in segment

  • Channel loss support up to 8dB

  • Supports both AC and DC

  • Standard two supplies and devices

  • Supports any lane configuration up to x20 per macro

  • No external components nor special packaging requirements

  • Integrates seamlessly with extensive test & configuration software and features

  • Available in advanced FINFET technology